FIG. 2 shows a schematic illustration of a known TAP controller.
In FIG. 2, reference symbol TAP designates a TAP controller (TAP=Test Access Port). Such a TAP controller is situated together with further integrated circuits, which are to be tested by corresponding test programs, on a chip. The TAP controller has an input Etdi for a test data signal tdi, an input Etck for a test clock signal tck, an input Etms for a test mode signal tms and an input Etrst for a test reset signal trst. The inputting of the test reset signal trst for the TAP controller is optional. The provided input Etrst for the test reset signal trst is recommended but is not absolutely necessary in accordance with the IEEE 1149.1 standard.
Also depicted in FIG. 2 is an output A for an output control signal for circuit components (not shown) to be tested.
The test data signal tdi is fed via a corresponding line from a test data signal pad Ptdi to the input Etdi. The test clock signal tck is fed via a corresponding line from a test data signal pad Ptck to the input Etck. The test mode signal tms is fed via a corresponding line from a test mode signal pad Ptms to the input Etms. Furthermore, on the chip of the known TAP controller, there is a pad Prst for an external reset signal reset_n, which can be supplied via a corresponding line to specific circuit components of the circuit components to be tested, in order to reset them in the context of a system reset.
FIG. 3 shows a state chart of the known TAP controller.
In FIG. 3, RST designates a reset state, RT designates a test state, DR1-DR7 designate data register states and IR1-IR7 designate instruction register states. The ones “1”, and zeros “0” associated with the respective arrows designate how the state changes cyclically when a corresponding test mode signal tms is applied to the input Etms.
In the concrete example, the states have the meanings listed in the table below:
DR1Selection dataIR1Selectionregister scaninstruction registerscanDR2Incorporation dataIR2Incorporation datain data registerin instructionregisterDR3Shift data registerIR3Shift instructionregisterDR4Output 1 dataIR4Output 1 instructionregisterregisterDR5Pause data registerIR5Pause instructionregisterDR6Output 2 dataIR6Output 2 instructionregisterregisterDR7Refresh dataIR7Refresh instructionregisterregister
By way of example, the status IR3, i.e. the status “shift instruction register” is reached from the reset state RST by means of the following serial data word, “01100”. As long as the “0” is held in the test mode signal, in the status IR3 the instruction register is shifted by one bit upon each clock cycle. The reset state RST is reached from the state “shift instruction register” IR3 by means of the signal sequence “11111”.
As can be seen from FIG. 3, more than five successive states logic “1” of the test mode signal are required for this synchronous resetting proceeding from no state.
However, in the case of certain applications and under certain preconditions, it would be desired to achieve a reset state of the TAP controller by means of a single clock cycle. This can be done, in principle, by inputting a logic “0” into the input Etrst for the test reset signal trst. TAP controllers without any inputting of a test reset signal trst have the following two disadvantages. Firstly, a simulation problem arises because, without the resetting, the TAP controller assumes an undefined state, and all the output signals are undefined in this case. The other problem is a hardware problem because the TAP controller can assume an undefined state on account of an unstable crystal frequency during switch-on and trigger an uncontrolled test mode which, depending on the test mode, could be cleared by a test reset signal trst with little complexity.
Although the TAP controller TAP can thus be reset asynchronously at the input Etrst for the test reset signal trst in a single clock cycle, the number of pads on a chip is limited for space reasons and/or cost reasons, and an additional pad for this test reset signal trst (indicated by broken lines in FIG. 2) is not possible in many cases. In cases where an additional pad is possible, the additional pad causes additional costs.
Secondly, the external reset signal reset_n cannot be applied to the input Etrst directly from the pad Prst present therefor, since such resetting can result in undefined states and, in accordance with the IEEE 1149.1 standard, it should not be possible to change the TAP controller state uncontrollably.
Therefore, it is an object of the present invention to provide a method for operating a TAP controller in which controlled asynchronous resetting is possible without the need for a further pad for a test reset signal.
According to the invention, this object is achieved by means of the method defined in claim 1 and the TAP controller specified in claim 4.